                                             
IBIS Macromodel Task Group

Meeting date: 09 Aug 2011

Members (asterisk for those attending):
Agilent:                    * Fangyi Rao
                            * Radek Biernacki
Altera:                       David Banas
Ansys:                        Samuel Mertens
                            * Dan Dvorscak
                            * Curtis Clark
Arrow Electronics:            Ian Dodd
Cadence Design Systems:       Terry Jernberg
                            * Ambrish Varma
Celsionix:                    Kellee Crisafulli
Cisco Systems:              * Mike LaBonte
                              Ashwin Vasudevan
                              Syed Huq
Ericsson:                     Anders Ekholm
IBM:                          Greg Edlund
Intel:                        Michael Mirmak
LSI Logic:                    Wenyi Jin
Mentor Graphics:            * John Angulo
                              Zhen Mu
                            * Arpad Muranyi
			    * Vladimir Dmitriev-Zdorov
Micron Technology:            Randy Wolff
NetLogic Microsystems:        Ryan Couts
Nokia-Siemens Networks:     * Eckhard Lenski
QLogic Corp.                * James Zhou
Sigrity:                      Brad Brim
                            * Kumar Keshavan
                              Ken Willis
SiSoft:                     * Walter Katz
                            * Todd Westerhoff
                              Doug Burns
Snowbush IP:                  Marcus Van Ierssel
ST Micro:                     Syed Sadeghi
Teraspeed Consulting Group:   Scott McMorrow
                            * Bob Ross
TI:                           Casey Morrison
                              Alfred Chong
Vitesse Semiconductor:        Eric Sweetman
Xilinx:                       Mustansir Fanaswalla

The meeting was lead by Arpad Muranyi

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Opens:

- James Zhou introduction:
  - Principal SI engineer at QLogic
  - Serdes and DDR3 simulations
  - Developing network storage ASICs and other network products
  - Created IBIS with home grown programs
  - Must provide models to customers, but using vendor provided AMI models

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Call for patent disclosure:

- None

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Review of ARs:

AR: Arpad update BIRD 135
  - Done

AR: Arpad update BIRD 137
  - Done

AR: Arpad update BIRD 127
  - Done last week

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New Discussion:

Arpad showed BIRD 137
- Arpad quickly described modifications
- Radek: It looks good
- Arpad: This has a single argument, which is not true
  - Walter had suggested new wording
- Radek: This looks looks good
- Bob: Agree
- Walter: One from each column could go in parentheses
- Bob: A note at the end should describe the changes
  - Say it is in response to BIRD 132
- Arpad: Can this be submitted?
- Ambrish: Would like more time to review
- Walter: We should submit
  - The next meeting is in two weeks
  - We can submit after the next ATM meeting

Walter showed "Components of an IBIS-AMI Simulation"
- Slide 3
  - The EDA tool generates the stimulus to TX GetWave
  - This must include jitter
  - IBIS 5.0 TX_Jitter specifies one of 4 jitter types
  - BIRD 123 added DCD, Rj, Sj+frequency
- Walter showed BIRD 123 with comments:
  - Clarification of DCD
  - Vladimir: This is more clear
  - Bob: Is there a need for Usage Out here?
  - Walter: We have not seen any
  - Walter: Rj is Gaussian
    - Vladimir had commented about "uncorrelated"
    - This is just a random distribution
    - Other spectral distributions could be described
  - Vladimir: The effect of jitter does depend on distribution
    - It could be uncorrelated or highly correlated
    - We should think about spectral distributions if this doesn't meet our
      needs
  - Walter: Some people call it bounded or deterministic jitter
    - Sj + Rj covers most needs
    - Dual Dirac and DjRj are forms of Sj
  - Kumar: DjRj is a post-process, Sj is time domain
  - Walter: There is C code that can generate Sj
    - Dual Dirac, DjRj and Table are not mathematically precise
  - Vladimir: Jitter amplification is very different for correlated jitter
    - Phase changes slowly from bit to bit when uncorrelated
  - Walter: Two effects
    - 1) Data dependent jitter could affect amplification
         - Out of the context of what we can do
    - 2) Complex patterns could be amplified differently
         - Up to the EDA tool to generate these at TX input
  - Vladimir: I can provide examples
  - Fangyi: Kumar is talking about autocorrelation
    - People look at the spectrum of the jitter trend on the scope
    - There is a flat noise floor
    - That is plugged into random jitter
  - Walter added this to BIRD 123
  - Todd: Someone said uncorrelated jitter is Gaussian?
  - Vladimir: Gaussian jitter could be correlated or uncorrelated
    - It can be characterized by spectral distribution
    - Or it can be described statistically in time domain
  - Walter: In statistical there is no time domain
    - We have to know where the clock is
    - Must combine effects of CDR and reference clock jitter
    - May lose some jitter amplification
  - Fangyi: The word "incorporate" may be better than "combine"
  - Radek: Does it currently say they are combined?
  - Vladimir: We should say all TX jitter inputs may affect ISI
  - Walter: The EDA tool may use any method to combine the jitters
- Back to slide 3 of "Components of an IBIS-AMI Simulation"
  - Walter: RX GetWave has the CDR logic
    - It is affected by:
      - The reference clock that drives CDR
  - Arpad: Are we trying to define what the EDA tool does for CDR?
  - Walter: No, the DLL does the whole job
    - The issue is when you have a forwarded clock
    - The clock channel may be of different length
    - Clock ticks could be from a PLL, analyzed at system level
  - Arpad: We have no way to send ref clock to DLL
  - Walter: Clock_times can be an input
  - Kumar: PCIe has a forwarded clock option
    - It is at a much lower data rate, a different beast
  - Walter: Scott had requested this
    - Not sure who would write a model to use this
  - Todd: Normally a ref clock is multiplied up
    - Is this ref at PCB level or for CDR?
  - Walter: It has to include the effects of everything else
  - Kumar: It has to all be in the Rx model
  - Walter: The slow clocks have 32 phases

AR: Arpad post BIRD 137 

Meeting ended.

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Next meeting: 16 Aug 2011 12:00pm PT

Next agenda:
1) Task list item discussions

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IBIS Interconnect SPICE Wish List:

1) Simulator directives
